Title :
Design verification problems: test to the rescue?
Author_Institution :
Veritable Inc.
fDate :
Sept. 30-Oct. 2, 2003
Keywords :
Automatic test pattern generation; Binary decision diagrams; Computer bugs; Fault detection; Formal verification; Integrated circuit modeling; Integrated circuit testing; Manufacturing processes; State-space methods; Virtual manufacturing;
Conference_Titel :
Test Conference, 2003. Proceedings. ITC 2003. International
Print_ISBN :
0-7803-8106-8
DOI :
10.1109/TEST.2003.1271132
