Strained Si/SiGe technology: status and opportunities

Author

Haensch, Wilfried

Author_Institution

IBM Res. Div., Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

2003

fDate

10-12 Dec. 2003

Firstpage

48

Abstract

Fabrication of sub-100 nm strained Si/SiGe MOSFETs using CMOS technology have been demonstrated, with current drives enhancements in both NFET and PFET. Material properties of strained Si and SiGe require careful modifications in CMOS process flow. Band offset induced shift in threshold voltages need to be compensated by device design and the difference in dopant diffusion properties also need to be taken into account. SGOI substrates can be fabricated by SIMOX, thermal diffusion of Ge and layer transfer techniques.

Keywords

Ge-Si alloys; MOSFET; SIMOX; carrier density; electron mobility; elemental semiconductors; hole mobility; silicon; thermal diffusion; 100 nm; CMOS process flow; CMOS technology; NFET; PFET; SIMOX; Si-SiGe; Si-SiGe MOSFET; band offset induced shift; carrier density; electron mobility; hole mobility; layer transfer method; thermal diffusion; CMOS technology; Dielectric materials; Dielectric substrates; Electron mobility; Germanium silicon alloys; MOSFETs; Research and development; Silicon germanium; Silicon on insulator technology; Tensile strain;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Device Research Symposium, 2003 International

Print_ISBN

0-7803-8139-4

Type

conf

DOI

10.1109/ISDRS.2003.1271989

Filename

1271989