Title :
A formal approach towards systems modeling and verification
Author :
Bhattacharyya, Joydeep ; Chaudhuri, A.R. ; Bhattacharya, Swapan
Author_Institution :
Dept. of Comput. Sci. & Eng., Jadavpur Univ., Kolkata, India
Abstract :
The paper introduces a new formal model, ASET (advanced system emulation technique), for systems modeling and verification. Our model tries to maintain, as far as possible, the structured approach, simplicity and hierarchy of DFDs (data flow diagrams) as well as drawing upon the control flow structure of Petri nets. This model clearly demarcates between data and control flow and simultaneously allows us to specify data dependent control conditions. Special consideration has been given towards modeling distributed systems, concurrent processes and integrity testing. A grammar for our model is also provided with some built in error checks.
Keywords :
Petri nets; data flow analysis; data flow graphs; systems analysis; Petri nets; advanced system emulation technique; concurrent processes; control flow; control flow structure; data flow diagrams; distributed systems; error checks; integrity testing; systems modeling; systems verification; Computer science; Control system synthesis; Control systems; Design for disassembly; Emulation; Engineering drawings; Maintenance engineering; Object oriented modeling; System analysis and design; System testing;
Conference_Titel :
TENCON 2003. Conference on Convergent Technologies for the Asia-Pacific Region
Print_ISBN :
0-7803-8162-9
DOI :
10.1109/TENCON.2003.1273309
