Analog sampled data architecture for discrete Hartley transform

This paper describes an analog VLSI architecture, capable of computing discrete Hartley transform (DHT), using basic analog blocks. The scheme operates from the general expression of DHT where the input samples are multiplied by all the DHT coefficients, simultaneously using a resistor string. These multiplied values are then switched in parallel with the help of a cross-point switch, to different integrators for performing necessary addition/subtraction. The proposed architecture is well suited where silicon area and power are required to be minimized with some compromise on accuracy.