DocumentCode
405601
Title
New protection structure against minority carrier injection
Author
Zitouni, M. ; de Fresart, E. ; de Souza, R. ; Lin, X. ; Morrison, J. ; Parris, P.
Author_Institution
SmartMOS Technol. Center, Motorola, Tempe, AZ, USA
fYear
2003
fDate
28-30 Sept. 2003
Firstpage
7
Lastpage
10
Abstract
In this paper, a simple and effective protection structure against minority carrier injection is proposed. The structure consists of an Nwell between the power device and the CMOS associated with a PBL (P buried layer) and an NBL (N buried layer) underneath the CMOS logic. The efficiency of this technique was evaluated in 2D and 3D device simulation.
Keywords
CMOS logic circuits; integrated circuit design; minority carriers; power semiconductor devices; semiconductor quantum wells; CMOS logic; N buried layer; NBL; Nwell; P buried layer; PBL; device simulation; minority carrier injection; power device; protection structure; CMOSFET logic devices; Charge carrier processes; Integrated circuit design; Power semiconductor devices; Quantum wells;
fLanguage
English
Publisher
ieee
Conference_Titel
Bipolar/BiCMOS Circuits and Technology Meeting, 2003. Proceedings of the
ISSN
1088-9299
Print_ISBN
0-7803-7800-8
Type
conf
DOI
10.1109/BIPOL.2003.1274925
Filename
1274925
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