Title :
Seamless top-down flow for quick trial of HW/SW co-design
Author :
Nojiri, Naotoshi ; Ishii, Tadatoshi
Abstract :
A design flow implementing a whole embedded system from the system-level C description to field-programmable devices is described. In this design flow, system-level models are seamlessly implemented and verified, thus turnaround time for system-level design and implementation is reduced, compared with the conventional design flow. As examples, this design flow is applied to two target architectures; as general-purpose processor core and a configurable processor core.
Keywords :
embedded systems; field programmable gate arrays; hardware-software codesign; reconfigurable architectures; system-on-chip; HW-SW codesign; configurable processor core; design flow; embedded system; field programmable devices; general purpose processor core; hardware-software codesign; quick trial; seamless top-down flow; system level C description; system level design; system level models; turnaround time; DVD; Design methodology; Embedded system; Graphical user interfaces; Hardware; Natural languages; Random access memory; Software tools; System-level design; System-on-a-chip;
Conference_Titel :
Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on
Print_ISBN :
0-7803-8320-6
DOI :
10.1109/FPT.2003.1275725
