Performance-driven recursive multi-level clustering

This paper presents an effective algorithm for multi-level circuit clustering for delay minimization, which is applicable to FPGAs. At the highest level of clustering, the circuit is clustered using a modified single-level clustering algorithm. A cluster to netlist transformation technique is proposed, which converts each cluster into a new subcircuit. The algorithm then continues recursively by clustering the generated sub-circuits into further levels of clusters. To reduce the amount to area overhead, a node duplication control algorithm based on the node slack is proposed and a cluster packing algorithm is used to reduce the number of clusters. Experimental results on the two-level clustering problem using Quartus Design System from Altera show that our algorithm reduces the delay, on average, by 7.3% compared with the best results in. Also the total FPGA compile time for all the benchmark circuits reported by Quartus is reduced by 36%.