Title :
Reconfigurable parallel comparation architecture and its application to IP packet filters
Author :
Aibe, Noriyuki ; Yasunaga, Moritoshi
Author_Institution :
Syst. & Inf. Eng., Tsukuba Univ., Japan
Abstract :
We propose a novel architecture for variable comparator named RPCA (Reconfigurable Parallel Comparation Architecture) making full use of the reconfigurability of FPGA. In the RPCA, an appropriate comparator to each task can be chosen and implemented under the speed/data-size tradeoff. An RPCA-based pack-filter prototype using XILINX XCV300E-6PQ240C and RealTeK RTL8201BL is developed and filtering speed of 120ns for 128 IPs and 1,360ns for 2,048 IPs are obtained under the speed/data-size trade-off.
Keywords :
comparators (circuits); field programmable gate arrays; parallel architectures; programmable filters; prototypes; reconfigurable architectures; FPGA; IP packet filters; RPCA; RealTeK RTL8201BL chip; XILINX XCV300E-6PQ240C chip; packet filter prototype; reconfigurable parallel comparation architecture; speed/data-size tradeoff; variable comparator; Buffer storage; Cryptography; Field programmable gate arrays; Information filtering; Information filters; Intrusion detection; Pattern matching; Prototypes; Spine; Systems engineering and theory;
Conference_Titel :
Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on
Print_ISBN :
0-7803-8320-6
DOI :
10.1109/FPT.2003.1275777
