A 3-D fast extractor for interconnect inductance of multiple right-hand sides

Author

Liu Yang ; Zeyi Wang

Author_Institution

Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China

Volume

2

fYear

2003

fDate

21-24 Oct. 2003

Firstpage

988

Abstract

With the development of VLSI circuits, the feature size has been decreased to the deep sub-micron level, and working frequency has reached 3GHz. IC performance depends directly on parasitic interconnect inductance and resistance. In this paper, we propose an improved filament refinement method based on fast multipole method (FMM). An improvement of setting right-hand sides is proposed to accelerate the convergence rate of the iterative method in solving multiple right-hand sides (RHS). Experimental results show that the extractor presented here runs tens to hundred times faster than the fastHenry with comparable accuracy.

Keywords

VLSI; circuit optimisation; inductance; integrated circuit design; integrated circuit interconnections; integrated circuit modelling; iterative methods; 3 GHz; 3-D fast extractor; FMM; IC performance; RHS; VLSI circuits; deep sub-micron level; fast multipole method; fastHenry; filament refinement method; interconnect resistance; iterative method; multiple right-hand sides; parasitic interconnect inductance;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2003. Proceedings. 5th International Conference on

ISSN

1523-553X

Print_ISBN

0-7803-7889-X

Type

conf

DOI

10.1109/ICASIC.2003.1277377

Filename

1277377