DocumentCode
405730
Title
A low power BIST TPG design
Author
He Ronghui ; Li Xiaowei ; Gong Yunzhan
Author_Institution
Inst. of Comput. Technol., CAS, Beijing, China
Volume
2
fYear
2003
fDate
21-24 Oct. 2003
Firstpage
1136
Abstract
This paper considers a BIST TPG that can highly reduce the power/energy consumption during test application without losing stuck-at fault coverage. Experimental results based on the ISCAS´85 and 89 benchmark circuits are reported to demonstrate the effectiveness of our approach.
Keywords
automatic test pattern generation; built-in self test; fault diagnosis; integrated circuit testing; low-power electronics; BIST; LFSR; TPG; WSA; benchmark circuits; built-in self-test; low power design; stuck-at fault coverage; test pattern generation; weighted switching activity;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2003. Proceedings. 5th International Conference on
ISSN
1523-553X
Print_ISBN
0-7803-7889-X
Type
conf
DOI
10.1109/ICASIC.2003.1277414
Filename
1277414
Link To Document