Title :
A low power BIST TPG design
Author :
He Ronghui ; Li Xiaowei ; Gong Yunzhan
Author_Institution :
Inst. of Comput. Technol., CAS, Beijing, China
Abstract :
This paper considers a BIST TPG that can highly reduce the power/energy consumption during test application without losing stuck-at fault coverage. Experimental results based on the ISCAS´85 and 89 benchmark circuits are reported to demonstrate the effectiveness of our approach.
Keywords :
automatic test pattern generation; built-in self test; fault diagnosis; integrated circuit testing; low-power electronics; BIST; LFSR; TPG; WSA; benchmark circuits; built-in self-test; low power design; stuck-at fault coverage; test pattern generation; weighted switching activity;
Conference_Titel :
ASIC, 2003. Proceedings. 5th International Conference on
Print_ISBN :
0-7803-7889-X
DOI :
10.1109/ICASIC.2003.1277414
