System level design methodologies from the viewpoint of formal verification

This paper gives a tutorial on system level design methodologies for system LSI, or System-On-Chip (SOC) designs and discusses about formal verification technologies targeting such system level specification/design descriptions. As a representative of system level specification/design language, we pick up SpecC language and introduce its associated design methodology for SOC designs. Although there are other system level specification/design languages, such as SystemC, the presented design methodology is basically shared with them. We also give an overview of the formal verification technology which can verify system level specification/design descriptions including verification of both hardware and software.