DocumentCode
405752
Title
Fast evaluation of symmetric-feasible sequence-pairs for analog topological placement
Author
Krishnamoorthy, K. ; Maruvada, S.C. ; Balasa, Florin
Author_Institution
Dept. of Comput. Sci., Univ. of Illinois at Chicago, IL, USA
Volume
1
fYear
2003
fDate
21-24 Oct. 2003
Firstpage
71
Abstract
Using nonslicing topological representations in device-level analog placement has recently gained interest since only feasible placements are analyzed, and since the number of devices in analog blocks is typically no more than 100 and, therefore, no scalability problem may occur. In this context, Balasa and Lampaert introduced the concept of symmetric-feasible sequence-pair in order to take into account during the exploration of the sequence-pair solution space the typical presence of symmetry groups of devices in analog designs. This paper presents a fast evaluation algorithm-of O(n log log n) complexity-for symmetric-feasible sequence-pairs, superior to the algorithm in having a quadratic complexity. Similar to Tang and Wong´s sequence-pair evaluation, this algorithm is based on the longest common subsequence computation, using an efficient priority queue data structure introduced by Johnson . A prototype analog placement tool based on this algorithm has been implemented. The novel approach exhibits significantly better computation times than other traditional analog placement techniques.
Keywords
analogue circuits; circuit complexity; evolutionary computation; analog designs; analog topological placement; computation times; device level analog placement; fast evaluation algorithm; feasible placements; nonslicing topological representations; priority queue data structure; prototype analog placement tool; quadratic complexity; subsequence computation; symmetric feasible sequence pairs;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2003. Proceedings. 5th International Conference on
ISSN
1523-553X
Print_ISBN
0-7803-7889-X
Type
conf
DOI
10.1109/ICASIC.2003.1277493
Filename
1277493
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