Standard-cell based data-path placement utilizing regularity

As more and more functions and operations are integrated into system-on-a-chip (SOC), data-path is becoming a critical part of the whole giga-scale integrated circuits (GSI) design. But the traditional placement tool cannot obtain satisfied result of data-path circuit because it has no knowledge of the data-path bit-slice structure and the parallel constraint. In this paper, an algorithm named DPP will be addressed to handle the standard-cell based data-path placement. It exploits the signal flow of circuit to generate the structure regularity of cells. Then, it converts the bit-slice structure to parallel constraints and partition policy so as to enable Q-Place algorithm on the placement. The design flow and the main algorithms will be introduced. Finally, the paper will discuss the satisfied experimental result of the tool compared with the Cadence placement tool SE.