The key technologies of performance optimization for nanometer routing

Routing plays an important role in VLSI/ULSI physical design. It is useful to develop advanced and efficient routers. The main nano challenge to routing is to perform "rigorous" performance optimization. The shrinking of geometry brings great concerns for chip performance. Interconnect effects cause longer delay. The decreasing of interconnect spacing has made the inter-wire coupling capacitance the dominant part of load capacitance, which causes longer delay and coupling noise (crosstalk). This paper discusses the key technologies of performance optimization for nanometer routing. One is the interconnect optimization, which includes delay/noise modeling and interconnect architecture. The other is the performance optimization for all nets routing, which focuses on multi-constraints optimization and multi-level optimization.