Two-dimensional common-centroid stack generation algorithms for analog VLSI

In analog VLSI design, two-dimensional common-centroid stacks, in which devices are two-dimensional symmetry and have a common-centroid, are critical for mismatch minimization and parasitic control. However it is difficult to construct due to several constrains of layout. In this paper, algorithms for generating analog VLSI two-dimensional common-centroid stack are described. We get several theory results by studying symmetric Eulerian graph and symmetric Eulerian trail. Based on those, an O(n) algorithm for dummy transistor insertion, symmetric Eulerian trail construction and two-dimensional common-centroid stack construction are developed. The generated stacks are two-dimensional symmetric and common-centroid. Several stacks with different ratio are generated for one group of devices and they could be chosen during placement according to the performance and area consideration. Experimental results show effectiveness of our algorithms.