Optimizing network on chip architecture size for applications

Network on Chip (NoC) is a new paradigm structure for designing future System on Chips (SoCs), where the cores communicate among themselves through an on-chip packet switched network. Many new tools will be required to help a designer develop applications using the paradigm. In this paper we describe an efficient two-step genetic algorithm for mapping parameterized multi task graphs, on to a NoC architecture with two dimensional mesh of switches as communication backbone. Our algorithm finds a mapping of multi task graphs´ vertexes to available IP cores on NoC so that every single task graph can meet its respective deadline. Our algorithm is able to handle large task graphs and provide near optimal mapping of task graphs to a fixed NoC architecture in a very short time. As one case, we show its effect on deciding an optimal size of NoC architecture for a given set of concurrent applications.