Recent advances in multicommodity flow algorithms for global routing

Interconnect planning and synthesis in general, and global routing in particular, are becoming critical to meeting chip performance targets in deep-submicron technologies. In addition to handling traditional objectives such as congestion, wirelength and timing. a new and very important requirement for current global routers is the integration with other interconnect optimizations, most importantly with buffer insertion and sizing. In this paper, we review and enhance a powerful integrated approach introduced in for congestion and timing-driven global routing, buffer insertion, pin assignment, and buffer/wire sizing. We extend the method to capture polarity constraints induced by inverter insertion, and present simpler and more efficient gadget constructions for buffer/wire sizing and enforcing delay constraints. Furthermore, we present experimental results detailing the scalability and limitations of proposed methods.