ETEM: an efficient gate and interconnect timing estimator considering cross-coupling for high performance layout

Conventional delay metrics are becoming more inadequate to handle new semiconductor process technologies and high performance design. We present in this paper a package of tools for accurate and efficient interconnect timing estimation, namely, ETEM, which combines a wire-load model and an interconnect delay model together with table-lookup method. It is capable of modeling parasitic effects and resistive shielding effects accurately, and taking into account the signal slew during delay evaluation. A probability model is adopted to estimate the wire spacing and a priority-queue-based algorithm is devised for timing computation. In our work, its application to performance-driven global routing is shown in comparison with the conventional analytical models.