Interconnect reuse based resource allocation with GA approach

With rapid development of technology, interconnect will occupy much chip area and gradually dominate circuit performance, interconnect optimization in high level design become more and more important. In this paper, we formulate an interconnect reuse based high level synthesis algorithm with GA (Genetic Algorithm) approach. The main contribution is that we put forward a novel coding method and design corresponding genetic operator for avoidance of generation of infeasible solutions. Experiments will show the efficiency of the algorithm.