Reliable buffered clock tree routing algorithm with process variation tolerance

As the clock frequency rises rapidly, clock skew has acted as a more important role in synchronous circuits. In this paper, we propose a new buffered clock tree routing algorithm to prevent the influence of process variations and environmental effects to clock skew. Based on the concept of BSF (Branch Sensitivity Factor), our algorithm manages to reduce the skew sensitivity of clock tree in topology generation. The worst case skew due to wire width change has been estimated, and proper buffers are inserted avoiding large capacitance load. Experimental results show that our algorithm can produce a more reliable, process-insensitive clock tree, and control clock skews in their permissible range evidently.