Parterre: an application-general SoC platform

Product complexity combined with smaller products size and shorter time-to-market (TTM), requires an effective IC design methodology. System-on-Chip (SoC) designs provide integrated solutions to solve the problems. The paper presents an application-general SoC platform-Parterre, which includes three sub-platform: 3-bus sub-platform, IP verifying sub-platform, system debugging sub-platform. The 3-bus sub-platform is the kernel and foundation of the Parterre, and the other two auxiliary sub-platform. The 3-bus sub-platform contains Integer Unit (IU), Floating-point Unit (FPU), Memory Management Unit (MMU) and three on-chip buses, etc. The IP verifying sub-platform is used to verify the IP blocks provided by third-party or designed by platform´s owner, the system debugging sub-platform provides an environment of system debugging. The Lilac chip is also presented, which is derived from the Parterre platform, used to control aerocraft and manufactured using TSMC 0.25-μm CMOS technology.