Parterre: an application-general SoC platform

Author

Yu Mingyan ; Xie Xuejun ; Wang Jinxiang ; Ye Yizheng ; Zhang Qingli

Author_Institution

Microelectron. Center, Harbin Inst. of Technol., China

Volume

1

fYear

2003

fDate

21-24 Oct. 2003

Firstpage

413

Abstract

Product complexity combined with smaller products size and shorter time-to-market (TTM), requires an effective IC design methodology. System-on-Chip (SoC) designs provide integrated solutions to solve the problems. The paper presents an application-general SoC platform-Parterre, which includes three sub-platform: 3-bus sub-platform, IP verifying sub-platform, system debugging sub-platform. The 3-bus sub-platform is the kernel and foundation of the Parterre, and the other two auxiliary sub-platform. The 3-bus sub-platform contains Integer Unit (IU), Floating-point Unit (FPU), Memory Management Unit (MMU) and three on-chip buses, etc. The IP verifying sub-platform is used to verify the IP blocks provided by third-party or designed by platform´s owner, the system debugging sub-platform provides an environment of system debugging. The Lilac chip is also presented, which is derived from the Parterre platform, used to control aerocraft and manufactured using TSMC 0.25-μm CMOS technology.

Keywords

CMOS digital integrated circuits; microprocessor chips; program debugging; system buses; system-on-chip; 0.25 micron; 3-bus subplatform; CMOS technology; FPU; IP verifying subplatform; IU; Lilac chip; MMU; Parterre platform; SoC platform; TTM; aerocraft control; floating point unit; integer unit; memory management unit; on-chip buses; product complexity; system debugging sub-platform; system-on-chip; time-to-market;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2003. Proceedings. 5th International Conference on

ISSN

1523-553X

Print_ISBN

0-7803-7889-X

Type

conf

DOI

10.1109/ICASIC.2003.1277575

Filename

1277575