Charge pump system sharing the coupling capacitors for NOR flash memory

A novel charge pump system sharing the coupling capacitors for NOR architecture flash memory is proposed in this paper. Two charge pumps operating alternatively can share the coupling capacitors. With the proposed technique, the chip size of the charge pump circuit is only about three fourths compared to the traditional circuit. In order to improve the performances of the negative charge pump, a special circuit is also designed to dynamically control the substrate bias of the PMOS transistors.