High-performance ROM design for embedded applications

In this paper we describe a CMOS Read Only Memory architecture designed for high performances and low power consumption using dynamic logic. A NOR-type structure ROM is designed using the wired-nor cell array and single-phase operational clock control. By using the precharge-discharge dynamic logic, the voltage swing of the bitline can be kept small, thus improve the operating speed and reduce the switching power. The single-phase operational clock also benefits the interfacing to other blocks in the ASIC. This architecture is well suited for memories embedded within ASICs or SOCs due to its excellent speed/power performance and is very convenient for implementation using typical CMOS ASIC Process. Simulation and fabrication results show that the designed 1 K words*28 bits Mask ROM works well as micro-code memory in the micro-programmed microprocessor.