A chaotic circuit for truly random number generation

In this paper, a chaotic circuit suitable for truly random number generation is proposed. The chaotic dynamical system used in the circuit is implemented based on the charge redistribution of capacitors. This method is better at area and power consumption than most of present methods. The prototype circuit has been fabricated in a standard 0.8 μm CMOS technology. The core size is less than 4200 μm² and power consumption is less than 1 mW.