Title :
An 8b 125Msamples/s 71mW A/D converter with 1.8 v power supply
Author :
Chen Cheng ; Ren Junyan ; Xu Jun
Abstract :
An 8b 125Msample/s pipelined A/D converter is presented, which operates at a single voltage 1.8 V. Power efficiency is optimized by size scaling down scheme using single stage amplifiers with gain boosted structure. Distributed clock generators are employed to avoid loss and overlap of clock period. The converter is implemented in 0.18 μm CMOS technology with a core area of 0.45 mm2. The total power dissipation is only 71 mW at full speed of 125 MHz. SIAND is 49.5 dB for an input frequency near Nyquist (Fin=62 MHz).
Keywords :
CMOS integrated circuits; analogue-digital conversion; integrated circuit design; 1.8 V; 125 MHz; 49.5 dB; 71 mW; CMOS technology; core area; distributed clock generators; gain boosted structure; pipelined A/D converter; power efficiency; single stage amplifiers; total power dissipation;
Conference_Titel :
ASIC, 2003. Proceedings. 5th International Conference on
Print_ISBN :
0-7803-7889-X
DOI :
10.1109/ICASIC.2003.1277633