Title :
A multi-gigabit CMOS serial link transceiver using jitter tolerant Delay Locked Loop
Author :
So, Byeong-Chun ; Hwang, Won-Suk ; Kim, Soo-Won
Author_Institution :
Dept. of Electron. Eng., Korea Univ., Seoul, South Korea
Abstract :
A multi-gigabit CMOS serial link transceiver is described. To reduce the jitter of the clock, it uses a multiphase Delay Locked Loop(DLL) when it receives the serialized data. The circuit operates with a parallel sampling technique to reduce the speed requirements of the circuits. The analog phase detector provides a linear characteristic while deserializing the data with no phase offset. The proposed circuit is designed using 0.25 μm CMOS technology. It is capable of recovering data at a speed of 2.5 Gbps.
Keywords :
CMOS digital integrated circuits; digital phase locked loops; phase detectors; transceivers; 0.25 micron; 2.5 Gbit/s; CMOS technology; DLL; analog phase detector; jitter tolerant delay locked loop; multigigabit CMOS serial link transceiver; multiphase delay locked loop; parallel sampling technique; Charge pumps; Circuits; Clocks; Delay; Detectors; Jitter; Phase detection; Phase locked loops; Sampling methods; Transceivers;
Conference_Titel :
Electron Devices and Solid-State Circuits, 2003 IEEE Conference on
Print_ISBN :
0-7803-7749-4
DOI :
10.1109/EDSSC.2003.1283508
