Title :
2D analysis of bottom gate misalignment and process tolerant for sub-100 nm symmetric double-gate MOSFETs
Author :
Shen, Jian ; Man, Tsz Yin ; Chan, Mansun
Author_Institution :
Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., China
Abstract :
The effects of bottom gate misalignment in symmetric double-gate MOSFETs are examined in this paper. Higher off-current and subthreshold swing is observed due to punchthrough at the bottom interface with bottom-gate misalignment. In addition, on-current reduction is also observed. The allowable bottom gate misalignment of very-deep-submicron devices due to process variation is studied, indicating the tighter process control required in the use of DG MOSFET compared with single-gate MOSFETs.
Keywords :
MOSFET; process control; semiconductor device models; tolerance analysis; 100 mm; 2D analysis; bottom gate misalignment; double-gate MOSFET; on-current reduction; process control; subthreshold swing; tolerant process; Back; Circuits; Degradation; Immune system; MOSFETs; Medical simulation; Process control; Semiconductor films; Silicon; Temperature control;
Conference_Titel :
Electron Devices and Solid-State Circuits, 2003 IEEE Conference on
Print_ISBN :
0-7803-7749-4
DOI :
10.1109/EDSSC.2003.1283514
