Leveraging delay slack in flip-flop and buffer insertion for power reduction

We show that the delay slack can be distributed optimally between flip-flops to reduce power in a pipelined interconnect, and such power reduction can be achieved by simultaneous flip-flop and buffer insertion satisfying latency and delay constraints specified at sinks. We develop a dynamic programming algorithm with effective pruning rules and pseudo polynomial time complexity with respect to the decimation and the length of a net. Experiments using a cluster of interconnect in a leading industrial high-performance design show that there exists plenty of useful slack for power reduction. Without jeopardizing the delay specification, as much as 17% of power can be saved for this cluster of interconnects.