Layout printability optimization using a silicon simulation methodology

The manufacturing complexity at the 90 nm and 65 nm technology nodes severely impacts the design. The traditional use of design rule based verification is no longer a guarantee of high yield once the chip has been manufactured. This paper describes many of the trends behind this phenomenon. A new approach to layout that moves from an abstraction approach to a modeling approach is proposed. In this new methodology, layouts are processed using resolution enhancement techniques and the results are simulated using lithographical models for a specific manufacturing process. The simulation results are used to identify critical regions in the layouts. The layouts are then optimized based on this analysis to improve their printability, manufacturability and yield.