Robustness enhancement through chip-package co-design for high-speed electronics

Low interaction between chip and package has more and more limited system performance. In this paper, chip-package co-design flow is presented. We address robustness enhancement under package and interconnection constraints by using impedance control, optimal package pins assignment and transmitter equalization. From the high-speed transmitter design example, co-design can reduce signal integrity problem, enhance its bandwidth, and improve high-speed electronic systems robustness.