A turbo decoder for high speed downlink packet access

The paper presents a new turbo decoder architecture, which uses an algebraic object known as a semi-ring, for high speed downlink packet access (HSDPA) in W-CDMA systems. By speeding up the state metric recursive operations in the BCJR algorithm with the help of semi-ring matrix algebra, this turbo decoder architecture can improve latency and throughput of about 10 Mbps, which cannot be achieved even with high-speed pipelined architectures. An implementation of the proposed architecture using ordinary commercially available FPGA demonstrates the reduced latency of the turbo decoder equivalent to the target throughput of 10 Mbps on 48 MHz clock frequency with 8 iterations without performance degradation, enabling efficient HSDPA data services.