Title :
Logical effort analysis of a media-enhanced adder
Author_Institution :
Cardiff Sch. of Eng., Cardiff Univ., UK
Abstract :
This paper assesses the delay and area penalties incurred by adapting a parallel prefix adder to implement a variety of multimedia-motivated operations. Specifically, a 64-bit adder´s delay is found to increase by 36% and its area by 23% if sub-word operand, average, saturating arithmetic, comparison, and min-max operations are supported.
Keywords :
CMOS logic circuits; adders; delays; logic design; network analysis; parallel architectures; 64 bit; 64-bit adder delay; PLX; instruction set architecture; logical effort analysis; media-enhanced adder; multimedia-motivated operations; parallel prefix adder; Added delay; Arithmetic; CMOS logic circuits; Capacitance; Costs; Instruction sets; Inverters; Minimax techniques; Process design; Technological innovation;
Conference_Titel :
Signals, Systems and Computers, 2004. Conference Record of the Thirty-Seventh Asilomar Conference on
Print_ISBN :
0-7803-8104-1
DOI :
10.1109/ACSSC.2003.1291933
