DSP system design using the BEE hardware emulation environment

This paper describes the design, analysis, and estimation features currently implemented in the Berkeley-Emulation Engine (BEE) system. BEE is an integrated rapid prototyping and design environment for communication and digital signal processing (DSP) systems. The hardware portion of the system consists of four multi-FPGA based processing units, each capable of emulating 10 million ASIC (application specific integrated circuits) equivalent gates at an overall system clock rate up to 60 MHz. The integrated software design flow enables the users to rapidly input the design using synchronous data-flow diagram, then automatically generates both the FPGA implementation for real-time rapid prototyping and a cycle-accurate, bit-true, and functionally equivalent ASIC implementation. The BEE design environment support rapid design turn-around and early performance analysis, without full synthesis or hardware mapping, from the high-level design entry.