Programmable code processor for software defined radio

Author

Perels, D. ; Bischoff, R. ; Biveroni, J. ; Bruehwiler, M. ; Burg, A. ; Felber, N. ; Fichtner, W.

Volume

2

fYear

2003

fDate

9-12 Nov. 2003

Firstpage

2156

Abstract

This paper describes a flexible processor capable of producing binary codes for various standards such as UMTS and 802.11b. Its field of application lies in base-stations and in future software defined radio terminals. Because of its flexibility just one or two instances may be integrated into a SoC (system on chip) where multiple codes are needed. This approach adds flexibility compared to a dedicated code generating structure where the class of codes is fixed. Specialized bit-ALUs allow to address multiple bits of a register and to operate simultaneously on them. Instructions tailored for code generation enhance its efficiency considerably. The processor was successfully integrated and tested in a 0.25 μm 5 ML CMOS process.

Keywords

CMOS logic circuits; binary codes; program compilers; shift registers; software radio; system-on-chip; 0.25 micron; CMOS process; SoC; arithmetic logic unit; binary code production; bit-ALU; code generating structure; programmable code processor; software defined radio terminal; system on chip integration; 3G mobile communication; Binary codes; CMOS process; Circuits; Code standards; Gold; Information technology; Logic; Multiplexing; Software radio;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 2004. Conference Record of the Thirty-Seventh Asilomar Conference on

Print_ISBN

0-7803-8104-1

Type

conf

DOI

10.1109/ACSSC.2003.1292362

Filename

1292362