A circular formulation of the prime length DHT kernel and its FPGA implementation

This paper presents a FPGA implementation of a one-dimensional prime-length discrete Hartley transform. The architecture for the hardware realization has been formulated to ensure maximum area and time efficiency. The presented design exploits the advantages presented by the distributed arithmetic and circular formulation techniques. Distributed arithmetic is very useful in creating efficient FPGA implementations while cyclic convolution provides the advantages of high computing parallelism, and low computation complexity. A single FPGA has been used to provide an area efficient design with a sampling rate of 12.5 million samples per second. The results indicate comparable speeds to that of the DCT.