DocumentCode
409877
Title
Efficient multithreading implementation of H.264 encoder on Intel hyper-threading architectures
Author
Ge, Steven ; Tian, Xinmin ; Chen, Yen-Kuang
Author_Institution
Intel China Res. Center, Intel Corp., Beijing, China
Volume
1
fYear
2003
fDate
15-18 Dec. 2003
Firstpage
469
Abstract
Exploiting thread-level parallelism is a promising way to improve the performance of multimedia applications running on multithreading general-purpose processors. This paper describes our work in developing the first multithreading implementation of the H.264 encoder. We parallelize the encoder using the OpenMP programming model, which allows us to leverage the advanced compiler technology in the Intel® C++ compiler for Intel hyper-threading architectures. We present our design considerations in the parallelization process. We describe an efficient multi-level data partitioning scheme that increases performance of a multithreaded H.264 encoder. Our experiments show parallel speedups ranging from 4.31x to 4.69x on a 4-CPU Intel Xeon™ system with hyper-threading technology.
Keywords
C++ language; multi-threading; program compilers; video coding; H.264 encoder; Intel Xeon™ system; Intel hyper-threading architectures; Intel® C++ compiler; OpenMP programming model; compiler technology; multilevel data partitioning; multimedia applications; multithreading general-purpose processors; thread-level parallelism; transform coding; Computer architecture; Decoding; Encoding; Hardware; Laboratories; Multithreading; Optimizing compilers; Parallel processing; Parallel programming; Program processors;
fLanguage
English
Publisher
ieee
Conference_Titel
Information, Communications and Signal Processing, 2003 and Fourth Pacific Rim Conference on Multimedia. Proceedings of the 2003 Joint Conference of the Fourth International Conference on
Print_ISBN
0-7803-8185-8
Type
conf
DOI
10.1109/ICICS.2003.1292496
Filename
1292496
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