DocumentCode :
411331
Title :
A novel ROM-less direct digital frequency synthesizer based on Chebyshev polynomial interpolation
Author :
Ashrafi, Ashkan ; Pan, Zexin ; Adhami, Reza ; Wells, B. Earl
Author_Institution :
Dept. of Electr. & Comput. Eng., Alabama Univ., Huntsville, AL, USA
fYear :
2004
fDate :
2004
Firstpage :
393
Lastpage :
397
Abstract :
In this paper a novel ROM-less direct digital frequency synthesizer (DDFS) is introduced. The phase-to-sine mapping section of this new scheme is designed based on approximation of the first half cycle of a cosine signal by a fourth order Chebyshev polynomial. The spurious free dynamic range (SFDR) of the proposed method is 64.2 dBc while the maximum achievable SFDR is theoretically obtained equal to 66.2 dBc. The proposed method is also implemented using the Xilinx Vertex-II FPGA and the experimental results exhibit the maximum clock frequency around 25 MHz.
Keywords :
Chebyshev approximation; direct digital synthesis; field programmable gate arrays; interpolation; polynomial approximation; signal processing; 25 MHz; Chebyshev polynomial interpolation; ROM-less frequency synthesizer; Xilinx Vertex-II FPGA; cosine signal; direct digital frequency synthesizer; first half cycle approximation; fourth order Chebyshev polynomial; maximum clock frequency; phase-to-sine mapping section; spurious free dynamic range; Chebyshev approximation; Circuits; Clocks; Energy consumption; Frequency synthesizers; Interpolation; Polynomials; Read only memory; Signal generators; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
System Theory, 2004. Proceedings of the Thirty-Sixth Southeastern Symposium on
ISSN :
0094-2898
Print_ISBN :
0-7803-8281-1
Type :
conf
DOI :
10.1109/SSST.2004.1295686
Filename :
1295686
Link To Document :
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