A novel low power pipelined architecture for a MC-CDMA receiver

This paper proposes a novel low power pipelined architecture for a multicarrier code division multiple access (MC-CDMA) receiver. The receiver is based on 64 subcarriers. It comprises of two blocks namely the FFT for demodulation and the combiner for despreading and equalization. The 64-point FFT block is based on low power pipelined radix-4 architecture in which coefficient ordering is applied to its second stage to further bring down its power consumption. Clock gating is extensively used in the combiner to reduce its power consumption.