DocumentCode
411501
Title
Efficient parallel finite field modular multiplier
Author
Li, Hua
Author_Institution
Dept. of Math. & Comput. Sci., Lethbridge Univ., Alta., Canada
Volume
1
fYear
2003
fDate
18-20 Sept. 2003
Firstpage
434
Abstract
In tins paper, a redundant canonical basis representation with the irreducible all one polynomial (AOP) is defined. Based on the proposed redundant representation, the multiplication operation can be simplified. A fast bit-parallel multipliers is proposed that require (m + 1)2 2-input AND gates and m(m + 1) 2-input XOR gates. The time delay is TAND + [log2(m + 1)]TXOR. The proposed architectures are highly modular and well suited for high speed VLSI implementations.
Keywords
VLSI; delays; logic gates; multiplying circuits; polynomials; 2-input AND gates; 2-input XOR gates; efficient parallel finite field modular multiplier; fast bit-parallel multipliers; high speed VLSI implementations; irreducible all one polynomial; redundant canonical basis representation; Computer science; Cryptography; Delay effects; Digital arithmetic; Embedded system; Galois fields; Mathematics; Polynomials; Signal processing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Image and Signal Processing and Analysis, 2003. ISPA 2003. Proceedings of the 3rd International Symposium on
Print_ISBN
953-184-061-X
Type
conf
DOI
10.1109/ISPA.2003.1296936
Filename
1296936
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