• DocumentCode
    411502
  • Title

    An intelligent hardware structure for impulse noise suppression

  • Author

    Louverdis, G. ; Andreadis, I. ; Papamarkos, N.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Democritus Univ. of Thrace, Xanthi, Greece
  • Volume
    1
  • fYear
    2003
  • fDate
    18-20 Sept. 2003
  • Firstpage
    438
  • Abstract
    In this paper an intelligent hardware module suitable for the computation of an adaptive median filter (AMF) is presented. The proposed digital hardware structure is pipelined and parallel processing is used to minimize computational time. It is capable of processing gray-scale images of 8-bit resolution with 3×3 or 5×5-pixel image neighborhoods as options for the computation of the filter output. However, the system can be easily expanded to accommodate windows of larger sizes. The function of the proposed circuitry is to detect the existence of impulse noise in an image neighborhood and apply the median filter operator only when necessary. Moreover, the noise detection procedure can be customized so that a range of pixel values is considered as impulse noise. In this way, the integrity of edge and detail information of the image under process is preserved and blurring is avoided. The proposed digital structure was implemented in FPGA and it can be used in industrial imaging applications, where fast processing is of the utmost importance. As an example, the time required to perform filtering of a grayscale image of 260×244 pixels is approximately 7.6 msec. The typical system clock frequency is 65 MHz.
  • Keywords
    adaptive filters; field programmable gate arrays; image denoising; image resolution; impulse noise; median filters; parallel processing; 65 MHz; FPGA; adaptive median filter; gray-scale images; impulse noise suppression; industrial imaging applications; intelligent hardware structure; noise detection; parallel processing; pixel values; Adaptive filters; Circuit noise; Computational intelligence; Concurrent computing; Gray-scale; Hardware; Image edge detection; Image resolution; Intelligent structures; Parallel processing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Image and Signal Processing and Analysis, 2003. ISPA 2003. Proceedings of the 3rd International Symposium on
  • Print_ISBN
    953-184-061-X
  • Type

    conf

  • DOI
    10.1109/ISPA.2003.1296937
  • Filename
    1296937