A fast and energy-efficient stack

Author

Ebergen, Jo ; Finchelstein, Daniel ; Kao, Russell ; Lexau, Jon ; Hopkins, David

Author_Institution

Sun Microsystems Labs., Mountain View, CA, USA

fYear

2004

fDate

19-23 April 2004

Firstpage

7

Lastpage

16

Abstract

We present some novel hardware implementations of a stack. All designs are clockless, fast, and energy efficient, while occupying modest area. We implemented a 42-place stack chip with a family of GasP circuits, making use of automatic transistor sizing and automatic layout generation. Results from simulations show that the chip will function correctly at speeds of up to 1.6 GHz in a 180 nm TSMC process. The cycle time of our stack chip is about 7 FO4 delays and is independent of the number of data items in the stack and the data width. The energy consumption per stack operation depends on the sequence of stack operations, but grows slowly with the number of data items in the stack.

Keywords

CMOS digital integrated circuits; integrated circuit design; timing; 180 nm; 42-place stack chip; FO4 delays; GasP circuits; TSMC; automatic layout generation; automatic transistor sizing; cycle time; data items; data width; energy consumption; energy-efficient stack; fast stack; stack designs; stack hardware implementations; stack operations sequence; Circuits; Clocks; Delay effects; Energy consumption; Energy efficiency; Hardware; Laboratories; Latches; Protection; Sun;

fLanguage

English

Publisher

ieee

Conference_Titel

Asynchronous Circuits and Systems, 2004. Proceedings. 10th International Symposium on

ISSN

1522-8681

Print_ISBN

0-7695-2133-9

Type

conf

DOI

10.1109/ASYNC.2004.1299283

Filename

1299283