Operating mode analysis of deep-submicron CMOS buffers driving inductive interconnects

The actual operation of a complementary metal-oxide-semiconductor (CMOS) gate driving long resistance inductance-capacitance (RLC) interconnects is investigated in this paper. Using the alpha-law model, inductance effects of long on-chip interconnects on the operating region of submicron CMOS line-driver transistors are analysed. The study demonstrates that both the linear and the saturation modes of operation may be equally present during buffer switching and thus neither saturation region nor linear region model can be used solely to characterise the operation of the transistors. A computationally efficient closed form expression for the portion of the switching time the MOS transistors of a line driver actually operate in the saturation region is also presented. Proposed formulae, particularly suitable for CAD tools implementation, is characterised by a 15% accuracy as compared to SPICE simulations for a wide range of line parameters.