Top-down and bottom-up approaches to stable clock synthesis

In this work we present and study bottom-up, or multiplicative, clock synthesis and compare it to a proposed and alternative top-down, or divisive, methodology. The focus of the work is on the short-term stability for each approach and the implications associated with frequency multiplication and division. The analysis and simulation demonstrate that for a common application, a top-down clock synthesis approach achieves similar stability performance when compared to bottom-up synthesis, while also being substantially simpler to implement.