Desynchronizer circuit in SDH system using digital PLL

Synchronous Digital Hierarchy (SDH) has become the most common transmission technique in data communication systems. The adoption of SDH in telecommunications provides an international interface standard which facilitates the interconnection of national networks, and also makes provision for the compatibility of transmission equipment from different manufacturers. One common problem associated with SDH is the phase jitter introduced in different point during data transmission In this work we describe a desynchronizer circuit that may be used in the TU-11 mapper to improve the system performance as regarding settling time and phase jitter This mapper acts to add and drop DS-1 signals from the TU-11. The main circuit in the desynchronizer is the clock smoothing circuit. The clock smoothing circuit is an All Digital Phase Locked Loop (ADPLL). The DCO (Digital Controlled Oscillator) output frequency is a modified by a proposed smoothing frequency dividing scheme that determines the value of the k-register used to choose the DCO frequency. The desynchronizer circuit was simulated by the DSP "System View" and the early results shown an effective reduction in settling time and other system performance.