A power optimized decimator architecture for cascaded sigma-delta analog-to-digital converters

This paper presents a new approach for an efficient decimator architecture for cascaded sigma-delta (ΣΔ) modulators. The special aspect of the presented structure is the effort to integrate the recombination logic for cascaded modulators in general and additionally a gain error correction for continuous time (CT) modulators in the first stage of the decimator. The design of an appropriate filter topology is derived, analyzed, and verified by simulations. The proposed structure is compared to a conventional implementation, thereby improving efficiency by decades.