A power optimized decimator architecture for cascaded sigma-delta analog-to-digital converters

Author

Becker, Markus ; Heiber, Knut ; Ortmanns, Maurits ; Manoli, Yiannos

Author_Institution

Freiburg Univ., Germany

Volume

2

fYear

2003

fDate

14-17 Dec. 2003

Firstpage

798

Abstract

This paper presents a new approach for an efficient decimator architecture for cascaded sigma-delta (ΣΔ) modulators. The special aspect of the presented structure is the effort to integrate the recombination logic for cascaded modulators in general and additionally a gain error correction for continuous time (CT) modulators in the first stage of the decimator. The design of an appropriate filter topology is derived, analyzed, and verified by simulations. The proposed structure is compared to a conventional implementation, thereby improving efficiency by decades.

Keywords

cascade networks; circuit simulation; continuous time filters; error correction; logic design; network topology; sigma-delta modulation; cascaded ΣΔ modulators; cascaded sigma-delta analog-to-digital converters; continuous time modulators; filter topology design; first decimator stage; gain error correction; power optimized decimator architecture; recombination logic integration; simulations; structure efficiency; Analog-digital conversion; Analytical models; Delta-sigma modulation; Energy consumption; Filters; Frequency; Logic; Noise shaping; Sampling methods; Topology;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on

Print_ISBN

0-7803-8163-7

Type

conf

DOI

10.1109/ICECS.2003.1301907

Filename

1301907