An efficient model checker based on the axiomatization of propositional temporal logic in rewriting logic

In this paper, we propose an efficient Model Checker for the Propositional Temporal Logic denoted by PTL. This logic is known to be well suited to verify electronic circuits and reactive systems. A typical verification problem consists of establishing formally a relationship between the specification of a software/hardware system and its implementation. In the sequel we show how a hardware designer should proceed to specify his design and prove its correctness using a PTL module under Maude System. A series of experiments have been conducted successfully on a well-known benchmark to prove the effectiveness of mixing temporal logic and rewriting logic techniques.