DocumentCode :
412986
Title :
A reconfigurable coprocessor for high-resolution image filtering in real time
Author :
Uzun, IS ; Amira, Abbes ; Bensaali, F.
Author_Institution :
Dept. of Comput. Sci., Queen´´s Univ., Belfast, UK
Volume :
1
fYear :
2003
fDate :
14-17 Dec. 2003
Firstpage :
192
Abstract :
Applications based on Fast Fourier Transform (FFT) such as signal and image processing require high computational power, plus the ability to experiment with algorithms. To try to meet the dual requirements of high performance and ease of development, in this work we present a High Level framework for the implementation of FFTs for real-time image processing applications. The frequency-domain (convolution-based) image filtering problem is targeted by developing an FPGA-based parametrisable environment based on the proposed parallel 2-D FFT architecture for real-time operation. Results show that the parallel implementation of 2-D FFT achieves virtually linear speed-up and real-time performance for large matrix sizes.
Keywords :
convolution; coprocessors; fast Fourier transforms; field programmable gate arrays; image processing; parallel architectures; reconfigurable architectures; FPGA-based parametrisable environment; convolution-based filtering; frequency-domain image filtering; high level framework; large matrix sizes; parallel 2-D FFT architecture; parallel algorithm; real-time image processing; reconfigurable coprocessor; Algorithm design and analysis; Convolution; Coprocessors; Field programmable gate arrays; Filtering algorithms; Flexible printed circuits; Frequency domain analysis; Hardware; Image processing; Libraries;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on
Print_ISBN :
0-7803-8163-7
Type :
conf
DOI :
10.1109/ICECS.2003.1302009
Filename :
1302009
Link To Document :
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