Power aware data type refinement on the HIPERLAN/2

Author

Dimitroulakos, G. ; Milidonis, A. ; Galanis, M.D. ; Theodoridis, G. ; Goutis, C.E. ; Catthoor, F.

Author_Institution

Electr. & Comput. Eng. Dept., Univ. of Patras, Greece

Volume

1

fYear

2003

fDate

14-17 Dec. 2003

Firstpage

216

Abstract

A power aware data type refinement performed on the data link control layer of the HIPERLAN 2 protocol is presented. Applying static and dynamic analysis on the initial specification code, the crucial data types in terms of memory access and storage are identified. Then proper data structures are selected and an efficient memory architecture is derived, meeting the time constraints and reducing the energy of the system memories. Experimental results show a reduction of the memory energy consumption up to 37% compared with the energy consumption of the memory architecture imposed by the initial specification code.

Keywords

data structures; distributed memory systems; local area networks; memory architecture; packet switching; protocols; queueing theory; storage management; HIPERLAN/2 protocol; data link control layer; data packet routing; data queuing; data structures; distributed memory organization; dynamic memory management; memory access; memory architecture; memory energy consumption reduction; memory storage; power aware data type refinement; specification code; Access protocols; Data structures; Design engineering; Energy consumption; Laboratories; Memory architecture; Memory management; Power engineering computing; Time factors; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on

Print_ISBN

0-7803-8163-7

Type

conf

DOI

10.1109/ICECS.2003.1302015

Filename

1302015