A dynamically-reconfigurable image recognition processor

Author

Maruo, Kazuyuki ; Ichikawa, Masayoshi ; Miyamoto, Naoto ; Karnan, Leo ; Yamaguchi, Takahiro ; Kotani, Koji ; Ohmi, Tadahiro

Author_Institution

Advantest Labs. Ltd., Miyagi, Japan

fYear

2004

fDate

26-30 April 2004

Firstpage

151

Abstract

Summary form only given. We introduce a new image recognition processor using a run-time reconfiguration (RTR) technology. A phase impulse response function (PIRF) is employed as an application for evaluating the performance of RTR architecture. By utilizing the RTR architecture effectively, a complicated image processing application such as PIRF can be implemented on a single processor. To achieve this, a dynamically-reconfigurable arithmetic logic unit (DRALU) is proposed. Simulation results show that our proposed processor using DRALU can execute the PIRF within 30 msec.

Keywords

image processing equipment; image recognition; multiprocessing systems; performance evaluation; reconfigurable architectures; dynamically-reconfigurable arithmetic logic unit; dynamically-reconfigurable image recognition processor; image processing application; phase impulse response function; run-time reconfiguration technology; Arithmetic; Brightness; Discrete Fourier transforms; Fourier transforms; Frequency response; Image recognition; Laboratories; Object detection; Shape; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel and Distributed Processing Symposium, 2004. Proceedings. 18th International

Print_ISBN

0-7695-2132-0

Type

conf

DOI

10.1109/IPDPS.2004.1303139

Filename

1303139