Build-in reliability analysis for circuit design in the nanometer technology era

Author

Liu, Zhihong ; Zhang, Weiquan ; Mu, Fuchen

Author_Institution

Cadence Design Syst. Inc., San Jose, CA, USA

fYear

2004

fDate

2004

Firstpage

205

Lastpage

210

Abstract

In this paper, the methodology of the reliability modeling and simulation for the state-of-the-art technology is presented. The extraction for HCI (Hot Carrier Injection) and NBTI (Negative Bias Temperature Instability) for both lifetime and aged model parameter method is discussed. The integration of these models into the transistor level and gate level simulation flow can be used by the designers to satisfy the reliability requirements.

Keywords

SPICE; hot carriers; integrated circuit design; integrated circuit modelling; integrated circuit reliability; nanoelectronics; SPICE; aged model parameter method; build-in reliability analysis; circuit design; device degradation; gate level simulation flow; hot carrier injection; lifetime model; nanometer technology; negative bias temperature instability; reliability modeling; reliability simulations; transistor level simulation flow; Aging; Circuit analysis; Circuit simulation; Circuit synthesis; Hot carrier injection; Human computer interaction; Integrated circuit reliability; Negative bias temperature instability; Niobium compounds; Titanium compounds;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design and Technology, 2004. ICICDT '04. International Conference on

Print_ISBN

0-7803-8528-4

Type

conf

DOI

10.1109/ICICDT.2004.1309946

Filename

1309946